CS-343 Assignment 2

This week’s assignment is to review combinational logic and to start working with a schematic entry tool for configuring an FPGA.

• Sections 1, 2, 3, and 5 of Appendix B of the textbook.
• My web page on Boolean Minimization
• My web page on Getting Started With Quartus

Your assignment is to implement one slice of the MIPS ALU developed in Appendix B of the textbook using Altera’s Quartus development system, and targeting Altera’s UP3 prototyping board. We’d like to implement the full 32-bit ALU, but I haven“t masterd the LCD dot matrix display yet, so there is no way to display the results.

When you finish the assignment, send an email message to me that includes your account name in the message body. I will then retrieve your Quartus project from your My Projects directory in the lab. Be sure you always log off whichever computer you work on in A-205 so your project will be copied back to the server, from which I will get it.

Note: The description of the development steps assumes you followed the in-class presentation from February 7. If not, you might want to ask questions on the course discussion forum to get help.

1. Start Quartus and click on the File -> New Project Wizard menu item to start a new project. Specify a directory under My Documents\My Projects as the project directory. I suggest you use the name ”ALU_Slice“. I suggest that you use the directory name as both the project name and again as the name of the top-level design entity for the project. The FPGA on the UP3 board is a Cyclone EP1C6Q240C8. You can select this part number from the list presented on the third page of the wizard, or you can use the filters (Any QFP, 240, 8) to help select the part.
2. Use File -> New to start a new schematic file. Draw the schematic with inputs named Ainv, Bneg, F0, F1, Ai, Bi, and Cin. Have two outputs named Ri and Cout.
   There are shortcuts you could use to build the circuit, but for this assignment you are to use only the logic primitives available in the ”logic,“ ”other,“ and ”pin“ folders, which appear under the primitives folder when you select symbols.
3. • Where you need a permanent connection to a logic value of zero (for the SLT input), use the gnd (ground) symbol under the ”other“ folder. If you find you need a permanent connection to a logic value of one, use the vcc symbol in the same folder.
   • The switches and pushbuttons come into the FPGA with inverted values (pushed or on will be a 0 and not-pushed or off will be a 1). The easiest way to deal with this is probably just to put inverters between the input pins and the rest of your circuit. (Except for Cin, you need both the normal and the inverted versions of all inputs anyway, so you can just connect each input to an inverter and remember that the input to the inverter is the complement of the switch or button setting and the output of the inverter is the actual value.)
   • If you are feeling adventuresome, you can draw a separate circuit to use as a building block inside your diagram. Just create a separate .bdf file, draw the circuit, and give meaningful names to the input and output pins. Save the file, and then use File -> Create/Update -> Create Symbol Files for Current File to save the file as a symbol. You will then find your symbol in the list of items you can insert under the AND gate toolbar button. Look above the quartus50 library in the list. Possibilities to consider are a 2x1 multiplexor, a 4x1 multiplexor, and a full adder.
4. Save the file as ALU_Slice.bdf in your project directory. Compile it and be sure there are no errors.
5. Assign pins to the inputs and outputs. (See below.)
6. Program the device and try it out!

Here is a list of the FPGA pins to which the various buttons, switches, and LEDs on the Altera UP3 board are connected. The last column gives the recommended ALU_Slice functions to use for each in this project.

Here are diagrams of a sample solution you may look at:

• ALU_Slice.bdf
• Full_Adder.bdf