Readings and Assignments
The exam will cover material from Chapters 2, 4, and 5 of the textbook. Assigments 5, 6, and 8 can serve as the study guides for the material from Chapters 4 and 5. So this page simply reminds you that we also covered material on the MIPS Instruction Set Architecture (ISA) from Chapter 2. This material is actually implicit background material for Assignment 5, but here it is explicitly stated:
The MIPS Instruction Set Architecture
- Memory organization
- Register File organization
- Instruction Formats: R, I, and J instruction fields and their roles
- Instruction algorithms. The "Green Card" will not be available.
- Verilog expression for Effective Address calculation
- Verilog expression for Branch Target Address calculation
- Verilog expression for Jump Address calculation
Exam Structure
Expect the usual mix of multiple-choice, fill-ins, and diagrams. Expect some diagrams to be provided, but possibly only Figure 4.24 from the textbook (augmented with timing values as in Assignment 5). Other Figures I like from Chapter 4 include 4.51 and 4.60. Assignment 8 mentions Figures 5.9 and 5.17. I like to use Photoshop to add or remove parts of Figures.
No electronic devices will be allowed, but you should expect to have to do calculations involving addition, subtraction, multiplication, division, powers of 2, and base-2 logarithms. If your calculations require more than a few decimal places, either you or I have made a mistake.
If a question provides enough information for you to calculate a numerical answer, then the numerical answer, with correct units, is required.
For example, if the question is, “What is the period of a 1GHz clock?” the correct answer is “1 nanosecond,” not “the time between pulses” or some other true but non-quantitative statement.