Readings and Assignments
The exam will be cumulative in the sense that you will need to remember material from the first part of the course in order to answer some of the questions. But material covered before the first exam will not be explicitly tested again.
- Textbook Appendix C, Sections C.7 through C.11
- Textbook Chapter 2 (review material)
- Textbook Chapter 4, Sections 4.1 through 4.3
- Assignment 4
- Class Notes
Topics
Disclaimer: There may be topics on the exam that I’ve forgotten to list here. If I update the list, I will post notices on the course forum and Twitter.
- Difference between combinational and sequential logic
- Anatomy of clock signals: positive edge, negative edge, period, frequency
- Sequential devices: Unclocked R-S Latch, Clocked R-S Latch, D Latch, D Flip-flop
- Finite State Machine model: state register and combinational logic
- Present state, next state, external inputs, external outputs
- State diagrams (circles and arcs)
- FSM timing: clock edges and minimum clock period
- Why latches cannot be used for state registers
- Number of flip-flops in state registers
- Clock skew: why flip-flops have enable inputs and what they do
- State table (truth table for an FSM’s combinational logic) design
- Register design: connections of clock, enable, and data inputs; data outputs
- Design and implementation of MIPS register file
- Names and purposes of all inputs and outputs
- Full MIPS vs. Assignment 4: number of wires for all inputs and outputs
- Register 0
- Reason for two read ports but only one write port
- Design of multiplexers with multiple outputs
- RAM: chip select input and tristate outputs
- RAM: purposes and numbers of bits for inputs and outputs
- RAM: construction of deep memories from shallow chips; address decomposition and decoding
- MIPS Instruction Set Architecture
- Memory capacity and addressing
- Three instruction formats
- The Program Counter (PC)
- MIPS single-cycle datapath: Inputs to the PC
- MIPS single-cycle datapath: Using ROM for instruction memory
- MIPS single-cycle datapath: Use of rs, rd, and rd fields
- MIPS single-cycle datapath: R[rs] and R[rt]
- MIPS single-cycle datapath: Op code and function code fields
- MIPS single-cycle datapath: Implementation of beq and bne instructions
- Calculation of Branch Target Address (BTA)
- Verilog notation for BTA
- Deciding whether to use BTA or not