CS-343 Assignment 8

The goal of this assignment is to become comfortable with the mechanisms and analysis of a cache memory systems.

Answer each of the questions below in the body of an email message.

The relevant reading assignment is sections 5.1, 5.2, 5.3, 5.5, and 5.8 of the textbook.

This is an extra-credit assignment that is also a study guide for part of the final exam. I will post my solutions some time on the day before the exam.

1. List the three parameters that vary along the levels of the memory hierarchy. For each parameter, tell whether it increases or decreases the closer a hierarchy level is relative to the processor.
2. Which of the parameters you listed in the previous question is the reason that not all of a computer’s memory is constructed using the memory technology with the shortest access time possible.
3. True or false: If one ignores the issue raised by the next question, each level of the memory hierarchy, except the lowest, contains a copy of part of the contents of the next lower level of the hierarchy.
4. How does the term inconsistency (page 466) relate to the answer to the previous question?
5. What is locality, and how does it relate to cache performance?

1. What is a multi-level cache?
2. What is the reason for having multi-level cache?
3. Define the terms hit rate, hit time, and miss penalty
4. Define the terms cache line and memory block. Are they related?
5. What is a cache line’s V Bit: where is it, and what does its value indicate?
6. What is a cache line’s tag?
7. What is a cache line’s data, and how does it relate to question M-4?
8. What is a cache memory’s associativity?
9. What is another name for a cache memory with an associative set size of one?
10. What is another name for a cache memory with an associative set size equal to the total number of cache lines?
11. What is the potential advantage of making the associative set size larger?
12. What is the potential disadvantage of making the associative set size larger?
13. What is the potential advantage of making the cache line size larger?
14. What is the potential disadvantage of making the cache line size larger?
15. What is the difference between write through and write back? (Be sure you know which is which.)
16. Do you understand Figures 5.9 and 5.17 well enough to reproduce them and/or to use them to explain the algorithm for detecting and handling cache hits?

Assume a computer has 2m bytes of main memory, 2l lines of cache, a block size of 2w words, an associative set size of 2a, 2b bytes per word of memory, and that memory is byte addressable.

Assume the computer has a two-level cache with a hit time for L1 of 1 clock cycle, an L1 miss penalty of 10 clock cycles, and an L2 miss penalty of 100 clock cycles.

Answer the following questions in terms of m, l, w, a, and b. On the exam, you will need to be able to do this and also to be able to calculate values given actual values for these parameters or for actual sizes given in the list of assumptions above. For example, if you were told the memory had 8 bytes per word, you should be able to tell that b is 3, and work from there.

1. How wide is a memory address?
2. How wide are the tag, index, word offset, and byte offset fields of an address? Note: the byte offset refers to the position of a byte within a word, and word offset refers to the position of a word within a block or line; the textbook calls the word offset the “block offset.”
3. How many sets are there?
4. What is the average access time (in clock cycles) if the L1 hit ratio is 0.90 and the L2 hit ratio is 0.85?

Send me email (vickeryatbabbage.cs.qc.cuny.edu) with “CS-343 Assignment 8” as the subject. Be sure to put your name in the body of your message.

Be sure your answers are in the body of your message, not in an attachment.