CS-343 Assignment 6

The goal of this assignment is to become comfortable with the mechanisms and analysis of a pipelined processor.

Answer each of the questions below in the body of an email message.

All questions are based on the pipelined MIPS processor design in the second part of Chapter 4 of the textbook.

1. Give the names, in order, of the pipeline stages.
2. List the structural elements for each pipeline stage. (A structural element is a significant logic block, such as an adder or memory, but not minor elements like multiplexers.)
3. List the names of all the pipeline registers and tell what information fields each one contains.
4. Tell what happens in each pipeline stage for each of the following classes of instructions:
   • R-Type
   • Branch
   • Jump
   • Store Word
   • Load Word

1. If the non-pipelined processor had a 1 GHz clock and the pipeline were perfectly balanced, what would be the speed of the pipelined processor’s clock?
2. What would be the latency to execute a single instruction using the pipelined design? Give your answer as the number of clock cycles it would take.
3. If there were no hazards, what would be the throughput of the pipelined processor? Again, use clock cycles as the unit of time.
4. Define the three types of pipeline hazards.
5. Define delayed branching and tell which type of hazard it deals with.
6. Define register forwarding and tell which type of hazard it deals with.

Send me email (vickeryatbabbage.cs.qc.cuny.edu) with “CS-343 Assignment 6” as the subject. Be sure to put your name in the body of your message.