Introduction
The Assignment
- The project directory must be My Documents\My Projects\5-Bit_ALU spelled, capitalized, and punctuated exactly like that in your TREE Lab profile directory. Make sure it is transferred correctly from one computer to another before you submit the assignment. You may make a copy of the 5-bit_ALU directory on your H:\ drive, but (a) you should back up your work onto an external drive for security, and (b) I will expect to find your project in the proper place on the server and will not get it from your home directory except in very unusual circumstances. (This is being written after a long day tracking down Assignment 2 projects that were in the wrong places; sorry for the rant.)
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There must be at least the following schematic diagrams in your project: a top-level testbed that uses a symbol for the ALU;
an ALU schematic that uses five copies of a symbol for an ALU bit slice; a schematic for the bit slice that uses a symbol for
your full adder from Assignment 2; copies of Full_Adder.bdf and
Full_Adder.bsf that you should copy from your Assignment 2 Full_Adder
directory into 5-bit_ALU. (It would be possible to reference the full adder files without
copying them, but I will delete your Assignment 2 files from my testing computer before getting your Assignment 3 files; so be sure
to make a copy of those two files in your directory for Assignment 3.)
If you decide you want an additional module, for the output mulitplexer for example, that is all right. But see below for an easier way to get that than to build your own out of AND, OR, and NOT gates. (The only reason you would want to do that would be to practice for the exam!)
- Use Switches 9-5 for the five A inputs; Switches 4-0 for the five B inputs, and Keys (blue push buttons) 3, 2, 1, and 0 for Ainvert, Bnegate, f1, and f0 respectively.
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Use Red LEDs 9-6 for Carry, Overflow, Negative, and Zero respectively. Use Red LEDs 4-0 for the 5-bit result.
Optional (not for the faint of heart)
An easier to read output scheme would be to use three of the seven-segment displays to show the condition code and result bits as three hexadecimal numbers. Use HEX3 (the leftmost display) to show Carry, Overflow, Negative, and Zero, Use HEX1 to show Result4, and HEX0 to show Result3-0. To do this, you will need to download hex2sevenseg.v, a Verilog program that converts four binary inputs into the 7 outputs needed to display hexadecimal digits on a seven segment display. Save hex2sevenseg.v in your project directory, add it to the project, and convert it to a symbol file the same way you convert schematic files to symbols. Then add three instances of this symbol to your testbed; connect the outputs to the appropriate DE1 pins, and connect the twelve inputs to the appropriate outputs of the ALU module. You will need to use bus wiring (see below) to pull this one off.
- Remember, you will need to invert the Key inputs (do it in the testbed) in order make them work right: they produce a 0 when pressed and a 1 when not pressed, just the opposite of what is required.
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So far you have used only “primitives” (gates and pins) from the Altera library to do your schematic, but Quartus also
provides several “megafunctions” to make your life easier. Two megafunctions of particular interest for this assignment
are the lpm_mux, which can be configured as a 4×1 mux for the output multiplexer in the
ALU bit slice, and the lpm_inv, which can generate all four inverters for the Key inputs in one
shot. They are both found in the megafunctions—>gates directory of the Altera libraries
under the
Symbol Tool. Both of them launch a wizard that you have to go through to configure the device you want; the wizard then generates
the files needed to implement the function and its symbol and to add them to your project.
The lpm_mux wizard lets you specify the number of data inputs your want (4 is the answer), and except for filling in that value, all you have to do is click the “Next” button until the wizard finishes and lets you place your customized mux in your schematic.
Using the lpm_inv function raises an issue we haven’t gone over, busses, so you might find it easier to do the project without using this feature. For this project, you need to create a 4-wire bus that will connect the four pushbutton pins to the Ainvert, Bnegate, f1, and f0 inputs to the ALU. This bus and the inverters would go in the testbed part of the project. I have updated the Using Quartus web page with a new section on bus wiring.
Submit The Assignment
- When you have finished testing your project and it works, send me an email to tell me that it is ready. I will copy the project from your profile directory on Oak and check it out.
- If you had romaing profile problems and your project exists only in your home directory, tell me that in the body of your email message.
- The subject line of your email must be CS-343 Assignment 3, spelled and capitalized just like that.
- Be sure to sign your email with your real name, especially if it is not totally obvious from the name of your email account, in order to receive credit for the assignment.
- Send your email to either Christopher.VickeryATqc.cuny.edu or vickeryATbabbage.cs.qc.cuny.edu — but not to both.
- See the course syllabus for grading and late homework policies.