CS-343 Assignment 6

This assignment is also a topic guide for the final exam. You can receive full credit for the assignment even if your answers are incomplete. I will publish the solutions on Tuesday the 16th, hopefully in time to be helpful as you prepare for the exam on the 18th.

Readings

Chapter 5: § 5.1—5.4. Note the material on Performance of Single-Cycle Machines starting on page 315, which was covered on in class, but not in the previous homework assignment.

Chapter 6: § 6.1—6.3. Also, Figure 6.26 in § 6.4 (page 403) is a good summary of what control information has to be carried forward in each pipeline state.

Chapter 7: § 7.1—7.2. Pay attention to the concept of the memory hierarchy and why cache hit ratios are so much better than you would expect from random processes.

Chapter 8: § 8.1—8.4; omit § 8.3. Understand the three components of disk access time; that mechanical movement of disks leads to enormously long access times compared to all electronic devices; the need for chipsets to manage busses with different speeds; bandwidth.

Questions for this assignment:

1. What determines the maximum clock speed that can be used in the single-cycle CPU design?
2. What determines the maximum clock speed that can be used in a pipelined CPU?
3. What is a “perfectly balanced” pipeline? How fast could the clock be made in a perfectly balanced pipeline of n stages compared to a single-cycle design of the same datapath?
4. What is the equation for the execution time of a program? Use three product terms on the right.
5. In the above equation, what is the CPI for a a single-cycle CPU design? For a pipelined design with n stages?
6. Answer Exercises 6.1 and 6.2 at the end of Chapter 6. Note that 6.2.b is essentially the same as Question 3 above. Note that whichever way you answer 6.1.a, you have to show how you compute speedup based on the equation in Question 4 above.
7. Name and define the three types of pipeline hazards. Give examples of how to reduce or eliminate all three.
8. How many pipeline registers are there for an n stage pipeline?
9. What control and data information is in each pipeline register for the five-stage pipeline used in the book?
10. What are the advantages and disadvantages of a very deep pipeline?
11. What do SRAM and DRAM stand for; which is faster; which is more dense; which is more suitable for cache; which is more suitable for main memory?
12. What is temporal locality, and how does it affect cache performance?
13. What is a cache hit; what is the hit ratio; what happens when there is a cache miss that causes the probability of a cache hit to be very high in the immediate future?
14. Is cache management done by hardware, software, or a combination of both?
15. What is the relationship between a cache line and a main memory block?
16. What housekeeping information is kept in a cache in addition to the actual cache data in each line?
17. Describe direct-mapped, set-associative, and fully-associative cache designs.
18. What is bandwidth? Calculate the bandwidth between main memory and the CPU if each access takes 100ps and transfers one word at a time. Be sure to use the correct unit of measure.
19. Calculate the bandwidth between a cache and main memory if each access takes 50ps and transfers 16 words at a time. Use the same unit of measure as in the previous question.
20. What is the average access time of a disk with a sector size of 1024 bytes and 200 tracks if it takes 2 msec to move from one track to another; the disk rotates at 7200 RPM; and the disk is connected to memory through a 512 MB/s bus. Assume seek time is not optimized by the operating system.
21. What bandwidth bus would be required to transfer an entire track from disk to memory using the disk described in the previous question if there are 1024 sectors per track?

I prefer receiving your answers as plain text in the body of your email message. If you use a word processor, paste your answers into the body of your message rather than sending an attachment.

Send your email to:

Christopher.VickeryATqc.cuny.edu

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