CS-343 Assignment 2

This assignment deals with basic skills related to combinational logic networks.

1. Design a Full-Adder, giving the implementation as a single truth table of two functions (Sum and Carryout) with three input variables (A, B, and Cin). Draw all the gates to implement the circuit using the Sum of Products technique presented in class.
2. Use a Karnaugh Map to minimize the Carryout function of a Full Adder. Write the minimized equation, and draw the gates to implement it.
3. 1. Give the truth table for a function with four input variables. The output is true for minterm numbers 4, 9, 11, 12, 13, 14, 15 (i.e., Σ { 4, 9, 11, 12, 13, 14, 15 } ).
   2. Minimize the function using both a Karnaugh Map and algebraic minimization. Be sure you get the same minimized function both ways.
   3. What is the Gate Input Count of the minimized function?
   4. Draw the gates needed to implement the minimized function.
   5. How many propagation delays are there in the logic network for the minimized function?
4. Draw a diagram that uses a symbol for full adders that shows how to construct a 4-bit parallel adder. Label all inputs, outputs, and the intermediate carries meaningfully.
5. What is the number of propagation delays in the four-bit adder network?

This assignment is to be written out on paper and handed in on the due date. If you do not have it ready at class time, you may leave in my office (SB A-222) any time before 6:15 p.m. on the due date. Just slip it under my door if I am not there.

Be sure to put your name on your assignment!