CS-343 Assignments 4a and 4b

This assignment is an exercise in Finite State Machine (FSM) design. It builds on the previous assignment, which was to implement a simple FSM that acted as a binary counter. For this assignment, you will add three external inputs to control the counter. Up will be a pushbutton which, when held, will cause the counter to count upward at a 1Hz rate, just like the previous assignment. The second input will be another pushbutton called Dn. When this button is pressed the counter is to count backwards (“down”). If neither button is pressed or if both buttons are pressed at the same time, the counter is to do nothing, just stay in whatever state it was last in. The third external input will be another button called Rst (“reset”). When this button is pressed, regardless of whether the other buttons are pressed at the same time or not, the counter is to reset; that is, all four flip-flops are to get the value 0000₂ on the next clock pulse.

This assignment consists of both written and practical components. For the written component, you are to draw a complete state diagram and state table for a ldquo;two-bit up-down counter with reset” FSM. Because there are only two state bits along with the three external inputs, your state diagram will have only four states (circles) and your state table will haveldquo;only” 2⁽³⁺²⁾=32 rows. Please order the columns in your state table as follows to make it easier for me to check. I’ve set up the whole table for you and filled in the first few rows to get you started. Note that the last sixteen rows can be collapsed into four rows because the values of Up and Dn are don’t cares (X) when Rst is true.

Rst	Up	Dn	Present State		Next State		LED_2	LED_1
			FF_2	FF_1	FF_2	FF_1
0	0	0	0	0	0	0	0	0
0	0	0	0	1	0	1	0	1
0	0	0	1	0	1	0	1	0
0	0	0	1	1	1	1	1	1
0	0	1	0	0	1	1	0	0
0	0	1	0	1
0	0	1	1	0
0	0	1	1	1
0	1	0	0	0
0	1	0	0	1
0	1	0	1	0
0	1	0	1	1
0	1	1	0	0
0	1	1	0	1
0	1	1	1	0
0	1	1	1	1
1	X	X	0	0
1	X	X	0	1
1	X	X	1	0
1	X	X	1	1

You are to submit this part of the assignment (“Assignment 4a”) on a piece of paper in class on the due date.

The second part of the assignment (“Assignment 4b”)is to implement the full 4-bit version of the “up-down counter with reset” FSM using the UP3 circuit board and Quartus development tools. Create a new project directory and top-level design named UpDnCounter in your My Projects directory, and implement the top-level design as a Block Diagram Schematic named UpDnCounter.bdf .

Implement the following truth table to convert three input pins into two intermediate values, which are named F₁ and F₀ in the truth table, but which don’t actually need names in your schematic:

Rst	Up	Dn	Function	F1	F0
0	0	0	Do Nothing	0	0
0	0	1	Down	0	1
0	1	0	Up	1	0
0	1	1	Do Nothing	0	0
1	X	X	Reset	1	1

Use four 4x1 multiplexers to supply the inputs to the four flip-flops, with the values of F₁ and F₀ connected to the two control inputs of all four multiplexers. You may use the following Verilog code to generate a single symbol for a “quad 4x1 mux”. (This Verilog code could be simplified by using arrays, but I’ve found that the resulting 4-bit busses for inputs and outputs are hard to work with in the schematic editor.) Alternatively, you could select the device “74153” from the megafunctions->others->maxplus2 library, which gives a symbol with two 4x1 multiplexers, but you will need two of them and they have an extra input (GN) that you have to connect to ground.
Here’s the Verilog:

      //  File quad_4x1_mux.v

      //  Quad 4x1 Multiplexer
      //  Ugly code, but listing all the I/Os individually
      //  makes use in schematics easier.

      module q4x1_mux (y0, y1, y2, y3,
                       a0, a1, a2, a3,
                       b0, b1, b2, b3,
                       c0, c1, c2, c3,
                       d0, d1, d2, d3,
                       sel_0, sel_1);

      output  y0, y1, y2, y3;
      input   a0, a1, a2, a3,
              b0, b1, b2, b3,
              c0, c1, c2, c3,
              d0, d1, d2, d3;
      input   sel_0, sel_1;
      reg     y0, y1, y2, y3;

      //  Update outputs anytime any input changes.
      always @(a0 or a1 or a2 or a3 or 
               b0 or b1 or b2 or b3 or
               c0 or c1 or c2 or c3 or
               d0 or d1 or d2 or d3 or
               sel_0 or sel_1)
        case ({sel_1,sel_0})
          2'b00:  begin
                    y0 = a0;
                    y1 = a1;
                    y2 = a2;
                    y3 = a3;
                  end
          2'b01:  begin
                    y0 = b0;
                    y1 = b1;
                    y2 = b2;
                    y3 = b3;
                  end
          2'b10:  begin
                    y0 = c0;
                    y1 = c1;
                    y2 = c2;
                    y3 = c3;
                  end
          2'b11:  begin
                    y0 = d0;
                    y1 = d1;
                    y2 = d2;
                    y3 = d3;
                  end
          // In case selector bits aren’t connected
          default:  begin
                    y0 = 1'bx;
                    y1 = 1'bx;
                    y2 = 1'bx;
                    y3 = 1'bx;
                  end
        endcase
      endmodule
      

Using the Verilog multiplexor, the a inputs are for F₁F₀=00, the b inputs are for F₁F₀=01, etc.

Use the following pin assignments for this project:

Clock	29
Rst	57
Up	49
Dn	48
LEDs 1, 2, 4, 8	53, 54, 55, 56

Use the Divide By 48M circuit from the previous assignment so that state changes will happen at a 1Hz rate. Be sure to test your circuit carefully, and remember that you will have to hold buttons for up to a second before they will do anything because of the slow clock rate going into the FSM.

Due Date and Submission