CS-343 Assignment 3

This assignment is to make the four LEDs on the UP3 blink!

• Sections 7, 8, 10, and 11 of Appendix B of the textbook.

Your assignment is to build a finite state machine that simply cycles through sixteen states at a rate of 1 Hz. You are to encode the sixteen states as 4-bit numbers using four flip-flops. Connect the outputs of the flip-flops to the four LEDs on the UP3 so that they will show a sequence of binary numbers 0000, 0001, 0010, 0011, ... 1111, and then back to 0000 again.

1. First you need to decide what kind of flip-flops to use for this project. The textbook goes through the development of a D flip-flop with a falling-edge trigger (Figure B.8.4). Quartus provides several types of flip-flops under the Primitives->Storage category. The one named dff is a D flip-flop with a rising-edge trigger, which is essentially the same as Figure B.8.4, but with an inverted clock input compared to the figure. The Quartus flip-flop also has two inputs name PRN and CLRN, which are asynchronous inputs that can be used to turn the flip-flop on (PRN, which stands for “PReset, Negated”) or off (CLRN, which stands for “CLeaR, Negated”) without the need of any clock signal. You’ll need to connect all the CLRN and PRN flip-flop inputs to Vcc (Logic 1) to disable their effects on your flip-flops.
   Quartus also provide J-K flip-flops and T flip-flops. If you are interested in a more efficient way to do the assignment, you could find out how T flip-flops work (the tff storage device in Quartus); they’re great for counter circuits like this one.
2. Create a .bdf file named Counter and put in four D flip-flops with their Q outputs connected to the four LEDs on the UP3. Connect an input pin name “Clock” to the clock inputs of all four flip-flops (the ones with the triangles next to them). For now, connect Clock to one of the push buttons.

   For this assignment, you may skip the full state-machine design and simply wire the flip-flops as described below. But it will help follow the description if you make a list of the sixteen possible states and what state the circuit goes into after a clock pulse. I’ll refer to the rightmost flip-flop as 1, the next one as 2, the next one as 4, and the leftmost one as 8 (corresponding to FPGA pins 53, 54, 55, and 56 respectively) in this table:

   Present State 8421	Next State 8421
   0000	0001
   0001	0010
   0010	0011
   0011	0100
   0100	0101
   0101	0110
   0110	0111
   0111	1000
   1000	1001
   1001	1010
   1010	1011
   1011	1100
   1100	1101
   1101	1110
   1110	1111
   1111	0000

   The heart of this design is to control whether flip-flops change state or not when they receive a clock pulse. With a D flip-flop we can do this by feeding the flip-flop’s Q output into its D input when we want it to stay in the same state, and by feeding the complement (not) of the Q output into its D input when we want it to “toggle” (change state, either from one to zero or vice-versa). If you think about the way a two-input XOR truth table works, you can see a way to set this up: connect the output of an XOR gate to the D input of a flip-flop, connect the Q output of the flip-flop to one input of the XOR gate, and the second input to the XOR gate becomes your toggle control. If it’s zero, the output of the XOR is the same as Q and the flip-flop doesn’t change, but if it’s one, the output is the opposite of Q and the flip-flop toggles.

   • Connect XOR gates to the D inputs of all four flip-flops, and connect the Q output of each flip-flop to one input of its XOR.
   • The rightmost flip-flop (flip-flop 1) is to toggle on every clock pulse, so connect its toggle control to logic 1 (Vcc).
   • Flip-flop 2 toggles only when flip-flop 1 is in its one state, so connect its toggle control to the Q output of flip-flop 1.
   • Flip-flop 4 toggles only when both flip-flops 1 and 2 are in their one states, so connect its toggle control to the output of an AND gate that has the Q outputs of flip-flops 1 and 2 as its inputs.
   • The logic for flip-flop 8 is left as an exercise!
3. Test this part of the design. Every time you press and release the button you are generating one clock pulse, and the LEDs should make one step through the sixteen states in binary counting order. But it won’t appear to work right! The buttons (and the slide switches too) are mechanical devices that work by moving a piece of metal so that it contacts another piece of metal (closing a circuit) or not (opening the circuit). But the moving piece of metal is spring-loaded so that it “snaps” open and closed, and it physcially bounces open and closed for a few milliseconds before coming to rest. The result is that every time you press or release the button your will get several pulses, and your counter will count very erratically. As long as the LEDs turn on and off in various ways as you press and release the button, you may assume the circuit is working okay. But if the LEDs don’t turn on or off at all, there is a problem that you need to fix before proceeding.

The UP3 provides several clock-generator circuits that produce streams of clock pulses at various frequencies. The one we will use operates at 48 MHz. It comes into the FPGA on pin number 29. You can start by changing the pin assignment for your Clock input and testing your design. But your four flip-flops will now go through their complete 16 state cycle 3 million times a second and the LEDs will just look like a dim blur. (Each flip-flop is on exactly half the time, so they will all appear half as bright as when they are fully on.)

You need to divide the 48 MHz clock signal on pin 29 down to a 1 Hz clock that you can use as the clock input to your flip-flops. You need a divide-by-n circuit that generates one pulse at its output for every n pulses at its input. In this case you need to divide the input clock by 48,000,000.

To build a divide-by-n counter, you connect ceil(log₂(n)) flip-flops as a binary counter that resets whenever the count reaches n. Or, equivalently, a counter that decrements from n to zero and then gets reset to n. (Either design is okay; I’ll use the latter, but you can do it the other way if you want to.) The leftmost flip-flop will toggle twice for every n input pulses, and the Q output of that leftmost flip-flop will be the output of the circuit.

Hmmm ... log₂(48000000) is 25.51653, which means we’ll need a binary counter with ceil(25.5) flip-flops: 26 of them!

It’s your choice: you can build a circuit with 26 flip-flops wired as a binary counter that counts backwards and with a circuit that constantly compares the values of the those flip-flops to all zeros and resets them to 10110111000110110000000000₂ when zero is detected, or you can create a new Verilog file named divide_by_48M.v and type the following code into it, which does the same thing. (In Quartus, use File->New and select Verilog HDL File instead of Block Diagram/Schematic File.)

Whether you decided to use a .v or a .bdf design for divide_by_48M, save it as a symbol using File->Create/Update->Create Symbol Files for Current File. (If you actually did decide to build the schematic, I need to have a talk with you!)

Insert an instance of this symbol into your Counter.bdf circuit, with the Clock input of your schematic connected to clockIn and dividedOut connected to the clock inputs of the four flip-flops.

Test your circuit and make sure it takes exactly 16 seconds for the LEDs to go through one complete cycle of the binary numbers 0000, 0001, ... 1111, 0000, ... .