latency: The time it takes for an instruction to emerge
from a pipeline after entering it.
throughput: The rate at which instructions are
completed.
bubble: A pipeline stage that is doing no useful work.
stall: The situation when one or more pipeline stages
repeat the same operation while waiting for a control or data hazard
to clear.
structural hazard: A limitation on parallelism due to
lack of hardware resources, such as arithmetic units or
interconnection pathways.
data hazard: A dependency between the generation of a
result and its use that must be accounted for in the design of a
pipeline.
control hazard: The possible execution of incorrect
instructions due to branch and jump instructions in a pipelined
datapath.
reordering: Changing the sequence in which instructions
are executed compared to the sequence in a program. May be done by
either a compiler or in hardware to reduce or eliminate data and
control hazards.
result forwarding: A technique for reducing or
eliminating data hazards in a pipelined design in which a result
is passed directly back to an earlier stage without waiting for the
instruction to pass completely through the pipeline.
delayed branch: A technique for reducing or eliminating
control hazards in a pipelined design in which the instruction
following a branch instruction is always executed regardles of
whether the branch is taken or not. Instruction reordering (see
above) is used to fill this "delay slot" with productive work
whenever possible, but if this fails a nop (no-operation)
instruction has to be used to fill the slot.
prediction: A technique for deciding which fork
following a branch instruction to feed into the pipeline in an
attempt to reduce pipeline stalls.
speculative execution: A technique in which both forks
following a branch are executed in parallel, and the unused fork is
discarded once the result of the branch condition has been
determined.
Question 2
5 GHz
It would be five times (400%) faster.
Question 3
IF/ID: 62 or 64 bits: Instruction (32) and PC+4 (32 or
30)
ID/EX: 114 bits: WB (2), M (2), EX (4), Read data 1&2
(64), Address/Immediate (32), and rt&rd (10)
EX/MEM: 72 or 74 bits: WB (2), M (2), Branch target (30
or 32), Zero bit from ALU (1), ALU result (32), and writeback
register number (5)
MEM/WB: 71 bits: WB (2), Mem data (32), ALU result (32),
and writeback register number (5).
Question 4
These two figures, and Figure 6.33 as well, do not show the
connection from the register file to the top Mux of the ALU.