This is a combination assignment and final exam preparation guide. As mentioned in class on 12/8, we don't have enough class meetings to cover all the material we "should" cover. So we'll skip some topics, cover some others more lightly that I'd like, and as usual will cover some material differently from the way it's done in the book. But most importantly, you are going to have to master some of the material on the final exam without the "benefit" of listening to me talk about it in class.
In addition to all of Chapter 6, you need to study the following parts of the textbook:
Chapter 7. You need to understand the principles of the Memory Hierarchy (pp 243-244). Study section 7.2; you need to understand the difference between static and dynamic RAM, how SRAM is implemented using gates and flip-flops. Use Section 7.3 to extend your understanding of Section 7.2 Figures 7-2 and 7-4 are important. You should already know the material in Section 7.5 (ROM). Section 7.6 introduces cache memory. You are responsible for all the material in this section through section 7.6.6, which ends on page 267. Section 7.6.5 is particularly important, but you need to know the material from earlier in section 7.6 to understand it.
Answer Problems 7.7, 7.8, 7.9, and 7.10.
a) Seven bits for the tag, 7 bits for the slot (line) number, and 4 bits for the word within the line.
b) Thirteen misses on the first loop iteration; 173 hits on the first loop; 9 * 186 =1,674 hits after the first loop. Total hits = 173 + 1,674 = 1,847. Total accesses (hits plus misses) = 1,847 + 13 = 1,860. Hit ratio = 1847/1860 = 0.993 (99.3%).
c) (0.993 * 10) + (0.007 * 210) = 9.93 + 1.147 = 11.4 nsec.
a) There are 216 / 23 = 213 blocks (lines) of main memory, so the tag field is 13 bits and the other three bits give the word within a line.
b) Addresses 20 (0000000000010 1002) are in block (line) 2, addresses 24 through 31 are in block 3, 32 through 39 are in block 4, and addresses 40 (0000000000101 0002 through 45 (0000000000101 1012 are in block 5. There will be (45 - 19) + 4 * (45 - 27) = 26 + 72 = 98 instructions executed. There will be four cache misses (the first time addresses 20,24, 32, and 40 are encountered) and 94 hits for a hit ratio of 94 / 98 = 0.959.
c) 0.959 * 40 + 0.041 * 1040 = 80.816 nsec.
Associative: 214 * ( (8 * 32) + 27 + 2) bits. Eight * 32 is the storage for each cache line; 27 is for each tag; 2 is for the valid and dirty bits.
Direct Mapped: 214 * ( (8 * 32) + 13 + 2) bits. The tags are reduced from 27 to 13 bits each because 14 of the 24 bits are used to select a specific cache slot.
a) The total number of words in the cache is 214 lines * 25 words per line = 219 words, so 219 is the minimum spacing to give a miss on every access.
b) In this case every access is a miss, so the effective access time is an even 1,000 nsec (1 microsecond).
Chapter 8. Read through section 8.3.3 (Direct Memory Access), which ends on page 313. In addition, study the UART Web Page.
There are many excellent Web Sites that cover the topics in Chapters 7 and 8. If you Google "northbridge southbridge" you can get started with some lecture notes that are available. And you will soon find links to sites that either point to other sites, or sites with real content. For example:
A problem with these links is that some of their reviews of the "latest and greatest" technology were written a couple of years ago and hence are no longer current. So as you read you need to keep your brain in gear and try to extract basic information and principles about how things work rather than pay too much attention about which particular device is the best of the lot.
Exercises: I'll post a copy of last semester's final exam, which has example questions.
The Blackboard Discussion Board has a special area set up discussions related to the final exam. I encourage you to use it! (But don't forget, Blackboard will be down Friday the 12th and possibly Saturday the 13th, so plan to work around that.)