Exam ID: 61103

1. What is the 8-bit two’s complement representation of –108₁₀? Answer in binary.

2. What is the two’s complement of your answer to Question 1? Answer in binary.

3. Add +43 to your answer to Question 1.

a) Give the sum in binary.

b) What is the value of the sign bit?

c) Was there overflow?

d) Was there a carry out of the leftmost position?

4. What is the IEEE-754 32-bit encoded representation of –108.375? Answer in hexadecimal. Show all work.

5. Give the truth table for a Full Adder.

6. Minimize the Carry_out function for a Full Adder using algebraic reduction and using a Karnaugh Map.

7. Construct a 4 ´ 1 multiplexor using inverters, AND gates, and tristate buffers.

8. What is the period of a 1.5 GHz clock? Be sure to indicate the proper unit of measure for your answer. (Hint: the unit of measure should be either microseconds, nanoseconds, or picoseconds.)

9. What is the frequency of a clock with a 4 nanosecond period? Be sure to indicate the proper unit of measure for your answer.

10. Draw a logic network that has the following characteristics:

a) There must be exactly three inputs.

b) There must be exactly one output.

c) There must be exactly three propagation delays (worst case) through the network.

d) There must be exactly five gates in the network.

e) No gate may have a fan-in greater than three.

f) The function implemented by the network may be any arbitrary function that meets the above criteria.