Serial Multiplier
Datapath
Recognizing that no more than one of Initialize, Add, and
Shift will ever be true at the same time, all the flip-flops
can be controlled by two bits, as follows:
|
|
| Shift Add Init
| x1 x0
|
| 0 0 0
| 0 0
|
| 0 0 1
| 0 1
|
| 0 1 0
| 1 0
|
| 1 0 0
| 1 1
|
|
Then, each register is controlled by x1 and
x0 as follows:
|
|
| x1 x0
| Register m
| Register C
| Register a
| Register q
|
| 0 0
| No Change
| No Change
| No Change
| No Change
|
| 0 1
| Load from A
| Load with 0
| Load with 0s
| Load from B
|
| 1 0
| No Change
| Load from C4
| Load from full adders
| No Change
|
| 1 1
| No Change
| Load with 0
| Shift right
| Shift right
|
|
Which leads to the following datapath design:
Controller
The state table for the controller would be:
|
|
| Inputs
| Outputs
|
| Present State
| Start
| q0
| Next State
| Init
| Add
| Shift
| Wait
|
| 0
| 0
| x
| 0
| 0
| 0
| 0
| 1
|
| 0
| 1
| 0
| 2
| 1
| 0
| 0
| 0
|
| 0
| 1
| 1
| 1
| 1
| 0
| 0
| 0
|
| 1
| x
| x
| 2
| 0
| 1
| 0
| 0
|
| 2
| x
| 0
| 4
| 0
| 0
| 1
| 0
|
| 2
| x
| 1
| 3
| 0
| 0
| 1
| 0
|
| 3
| x
| x
| 4
| 0
| 1
| 0
| 0
|
| 4
| x
| 0
| 6
| 0
| 0
| 1
| 0
|
| 4
| x
| 1
| 5
| 0
| 0
| 1
| 0
|
| 5
| x
| x
| 6
| 0
| 1
| 0
| 0
|
| 6
| x
| 0
| 8
| 0
| 0
| 1
| 0
|
| 6
| x
| 1
| 7
| 0
| 0
| 1
| 0
|
| 7
| x
| x
| 8
| 0
| 1
| 0
| 0
|
| 8
| x
| x
| 0
| 0
| 0
| 1
| 0
|
|
Assuming we decode the Present State to generate the intermediate values
State0 ... State8 we can derive the
following equations for the output variables, where Di
is the D input of the ith bit of the the 4-bit state register:
- Init = ( State0 ⋅ Start )
- Add = ( State1 + State3 +
State5 + State7 )
- Shift = ( State2 + State4 +
State6 + State8 )
- Wait = ( State0 ⋅ ~Start )
- D0 = ( q0 ⋅
( State0 + State2 + State4+
State6 ) )
- D1 = ( ( Start ⋅ State0
⋅ ~q0 ) + State1 + (
State2 ⋅ q0 ) +
( State4 ⋅ ~q0 ) +
State5 + ( State6 ⋅
q0 ) )
- D2 = ( ( State2 ⋅
~q0 ) + State3 + State4 +
State5 + ( State6 ⋅
q0 ) )
- D3 = ( ( State6 ⋅
~q0 ) + State7 )
Here is a logic diagram for the controller: