Final Exam Study Guide

Here are some exercises from Chapter 3 that would be good to look at: 22, 23, 24, 25, 26, 27, 32, 35, 37, 40.

Chapter 4: 2, 3, 4, 9, 10, 17.

Exam Topics

• You will be supplied with copies of Figures 3-37a (but not 3-37b), and 4-5 during the exam.

• You should be able to reproduce Figure 3-29 for any number of words and any number of bits per word.

• You should be able to tell how CS, RD, OE, I_i, and O_i would be used to perform reads, writes, and nops (no-operation).

• You should be able to show how to assemble SRAM ICs (like the one in Fig. 3-29) and a decoder to build a memory system, given the number of words and the number of bits per word in both the ICs and the memory system.

• You should be able to draw an implementation of a multiplexer using a decoder and tristate buffers. (The outputs of the decoder are the control inputs of the buffers; the data inputs to the multiplexer are the inputs to the buffers; the control inputs to the multiplexer are the inputs to the decoder.)

• You should know the differences between SRAM and DRAM with regard to speed and cost.

• You should be able to calculate the effective speed of a memory system given the cache hit ratio (CHR), the access time for cache (T_c), and the access time for main memory (T_m). (Effective Access Time = CHR * T_c + (1 - CHR) *T_m; Effective Speed = 1 / Effective Access Time.)

• You should know the relationship among the unclocked data memory, a memory controller, and a clocked memory bus.

• You should be able to answer questions like the ones in the exercises pertaining to Figure 3-37.

• You should know how a device controller (DC) and a device unit (DU) connect to the processor using an I/O bus. You should know the three types of registers in a DC, you should know the relative speeds of transferring information between the CPU and a DC compared to transferring informatin between a DC and a DU.

• You should know the difference between polled and interrupt-driven I/O, and you should know the role of the 8259A Interrupt Controller in Intel-based systems.

• You should know the principle of Direct Memory Access, and the two ways in which it improves performance of a system. You should also be able to answer questions like Question 40 at the end of chapter 3 pertaining to the impact of DMA transfers on CPU speed.

• You should know the approximate clock speeds of ISA, PCI, frontside, and backside busses. (A frontside bus, like PC66, PC100, PC133, or DDR, is used as the memory/local bus; a backside bus runs at the CPU clock speed and connects the CPU to cache, somewhat of a simplification of Figure 3-50.)

• You should be able to compute the bandwidth of a bus given its clock speed, the number of bits or bytes per transfer, and the number of clock cycles per transfer. (Bandwidth, in bits per second, is the bits per transfer times the clock speed in MHz, divided by the clock cycles per transfer.) Be sure to be able to convert to the proper units of measure.

• You should be able to reproduce Figure 4-2.

• You should be able to describe the use of the MAR and MDR registers in read/write operations of the IJVM.

• You should be able to describe the use of the PC and MBR in instruction fetch operations of the IJVM.

• You should be able to show how the bits in the MIR connect to the bits of the registers in the IJVM.

• You should be able to translate any of the microinstructions in Figure 4-17 into binary. In many cases you would have to be provided with the address of the next microinstruction explicitly. (See sample question below.)

• You should be able to write a sequence of microinstructions to perform a specific operation, like Exercise 17 at the end of chapter 4.

• You should be able to explain the role of control store in the IJVM CPU.

• You should be able to explain the relationship between the MBR and the addresses of microinstructions in the control store of the IJVM CPU.

Sample Question

    iadd1: MAR = SP = SP - 1; rd
    iadd2: H = TOS
    iadd3: MDR = TOS = MDR + H; wr; goto Main1

Answer