Study Guide for Exam 3

December 22, 1998

The exam will cover the material in Appendix B, including latches, flip-flops, register file design, and memory system design (using my memory system design web page as a supplement). It will also cover Chapter 5 up through Section 5.4.

There will be special emphasis on Figures 5.21, 5.33, 5.34, 5.42, and 5.43. We also covered Figures C.3 and C.5 from Appendix C as well as pages C-8 through C-13.

Sample Questions

  1. Tell what values would be loaded into each of the registers of the multi-cycle design at the end of State 1. Explain how each value is determined.
  2. An implementation of the MIPS datapath requires 2 nsec to access memory or to do an ALU/adder operation, and 1 nsec to read or write the register file. Assume the following instructin mix: 24% loads, 12% stores, 44% R-format instructions, 18% branches, and 2% jumps. Assuming that the multiplexors, control unit, PC accesses, sign extension unit, and wires have no delay, how long would the clock period be for the two designs developed in Chapter 5 (one clock per instruction and multiple clocks per instruction). What would be the average CPI for the two designs? Which design would be faster, and by how much?
  3. Draw a circuit that implements the "Sign extend" ovals in Figures 5.21 and 5.33