CS-341 Homework Solutions, Spring 1997

I have removed the answers to the textbook exercises. It's not a good policy for me to publish them on the web, since instructors at other schools might not want them to be public. In the future, I will email solutions to students in the course.

1. February 7
Exercises 2.14, 2.15, 2.16, 2.17, 2.18, 2.19.

2. February 11
Exercises 3.19 and 3.20. Extra: 3.21.

3. February 21
Translate the instruction "beq 3,4,somewhere" to hexadecimal. Assume the instruction is at decimal address 1020 and that the label "somewhere" represents decimal address 996.

    Since the PC register will have been incremented by four when the
    instruction is executed, the target address will be 996 - 1024 =
    -28, which must be divided by four to convert the distance from
    number of bytes to number of words between the target and the PC.

        Field   Width  Value  Binary
        Op code  6      4     000100
        rs       5      3     00011
        rt       5      4     00100
        Address 16     -7     1111 1111 1111 1001
        
        Binary instruction, 4 bits per group:
            0001 0000 0110 0100 1111 1111 1111 1001
        Hex:   1    0    6    4    F    F    F    9
4. February 28
Exercises B1, B2, B3, B4, B5, B6, B10, B11, B12.

5. March 25
Do Exercise 4.1. Translate 1.23 into a single-precision IEEE-794 floating-point number.

       1.23:              0x3F9D70A4 (last bit is rounded up)
6. March 28
Implement a ~S ~R latch using four NAND gates. Draw a "truth table" to describe its operation, and draw a timing diagram to illustrate its behavior.

  We went over this one carefully in class on April 4.
7. April 11
Complete the design of a 32M x 12 memory system using 8M x 4 SRAM ICs that was begun in class on April 8.

You should have a matrix of four rows and three columns of SRAM ICs. There are 25 Address lines; 23 go to each of the SRAMs, the other two go to a 2x4 decoder, whose outputs go to the CS inputs of all the SRAMS in a row. See the Memory System Design web page for an example of how to label everything.
8. May 2
Complete the table showing the settings of various control signals for different instructions that was begun in class on April 29.

RegDst Mem2Reg RegWrite ALUSelB f MemRead MemWrite
lw 0 1 1 1 010 1 0
sw X X 0 0 010 0 1
add 1 0 1 0 010 0 0
sub 1 0 1 0 110 0 0
and 1 0 1 0 000 0 0
or 1 0 1 0 001 0 0
slt 1 0 1 0 111 0 0
Dr. Christopher Vickery
Computer Science Department
Queens College of CUNY