1. Complete the following table for the single-clock-per-instruction datapath given in Figure 5.33.

2. Assume it takes 10 years to read a word from instruction memory, 5 years to read or write one of the registers in the register file, 10 years to perform an ALU operation, and 10 years to read or write a word of data memory.

1. How long would the clock period be using the design from Figure 5.33.
2. How long would it take to execute a 1,000 instruction program using this design.
3. How long would the clock period be using the design from Figure 5.39.
4. How long it would take to execute each of the following instructions using the design from Figure 5.39. Part of Figure 5.47 is on the blackboard. Instructions: lw, sw, beq, add, sub, and, or, slt. Show all work.
5. How long would it take to execute a 1,000 instruction program using the design from Figure 5.39 if the program has 25% loads, 10% stores, 50% R-type instructions, and 15% branches. Show all work.
6. How much faster would the program run using the design from Figure 5.39 instead of the design from Figure 5.33.

3. Complete States 2, 3, 4, and 8 for Figure 5.47.

4. You may draw a diagram to answer this question, provided you label it carefully.

1. Tell where the ten inputs to the finite state machine controller for the datapath would come from. Hint: there are two parts to this answer.
2. Tell where the 21 outputs from the finite state machine controller for the datapath would go to. . Hint: there are two parts to this answer.

5. Assume a PLA is used to implement the combinational logic portion of the finite state machine controller for the MIPS datapath. Show the portion of this PLA that would generate all the outputs for States 2 and 9. Hint: you will need 3 vertical lines. The op code for lw is 35₁₀, the op code for sw is 43₁₀, and the op code for j is 2₁₀.

6. List all the parts of the MIPS datapath (Fig. 5.39) to which the clock signal would be connected.