Here is a list of operation codes and function codes for some MIPS instructions. All values are in decimal:

1. (a) Translate this assembly language instruction into binary:

lw $13, 0xFFFC($5)

(b) Assume register 5 contains the value 0x50000. What memory address would be loaded into register 13 when this instruction executes?

2. (a) Translate this assembly language instruction into binary:

bne $20, $30, 5

(b) Assume the PC contains the value 0x40000 when this instruction is fetched from memory. What will be the branch target address for this instruction?

3. (a) Translate this assembly language instruction into binary:

slt $15, $16, $17

(b) What will be loaded into register 15 if register 16 contains 0xFFFFFFFF and register 17 contains 0x00001234 when this instruction is executed?

4. What is the disadvantage of the single clock-per-instruction datapath design developed in the textbook compared to the multiple clock-per-instruction design? Explain your answer.

5. Draw the instruction decode gates for the set of instructions listed at the beginning of the exam. There should be one output named R-type plus one output for each of lw, sw, bne, and j. You do not have to generate the ALUop signal (or any others). Label all inputs to show where they come from.

6. The signal ALUSelB is a two-bit value that controls the bottom input to the ALU (See Figure 5.39). Tell one situation in which each possible setting of these two bits would be used.

7. Explain the purpose of the RegDst control signal in Figure 5.39.

8. In the Figure 5.47, State 0 is named "Instruction Fetch." List the settings of all control signals that would be asserted in this state.

9. Draw all the gates to implement one bit of an SRAM IC. Label all inputs and outputs.

10. Draw a diagram that shows the names and number of wires for all inputs and outputs of a 16Mx4 SRAM IC.

11. Show how a 32Mx12 memory system could be constructed using 16Mx4 SRAM ICs. Label all inputs and outputs, and be sure to show how many wires go to each place.