- Give the IEEE-754 representation of the numbers +12.5 and 625.375.
Show all work. Answer in hexadecimal.
- What is the difference between a latch and a flip-flop.
- (A) Draw a block diagram for a 4x3 RAM IC. Label all inputs and
outputs meaningfully. (B) Draw the gates to implement a clocked D
latch. (C) Using clocked D latches like the one in your answer to part
B as building blocks, implement a 4x3 RAM IC. Be sure inputs and
outputs match your answer to part (A). Use tristate buffers to connect
outputs as needed.
- (A) Draw the gates and fuses to implement a 4x3 PROM. (B) Program
your PROM so that each word contains a numerical value equal to two
times its own address (unsigned). Include a legend to show whether a
fuse is present or blown.
- Figure 5.39 shows a Mux connected to the bottom of the ALU. Draw a
diagram that shows the internal structure of this Mux. Use a block to
represent each multiplexor (not the gates inside the multiplexors), and
show the connections between the control wires, the input wires, and
each of the multiplexors. Label all inputs and outputs meaningfully.
NOTE: Parts of your diagram are repeated several times. You need to
draw these parts just enough times (2-3) to show the pattern of
connections and the number of occurrences of the parts.
- (A) Draw the circuitry inside the "Sign extend" oval of
Figure 5.39. (B) Explain how this circuitry is used in load and
store.
- Draw a diagram that shows how to modify Figure 5.39 to support
bne as well as beq instructions. (Answer in your exam
book, not on the figure. Just draw the parts that have to be changed,
not the whole diagram.)
- List the names and values of the signals that would be asserted
during states 0 (8 signals), 6 (3 signals), and 9 (2 signals) in Figure
5.47.
- In addition to the six op code bits shown as inputs to the
"Control" oval of Figure 5.39, there are four other inputs
coming from four state flip-flops. (A) Draw a diagram that shows how
the state flip-flop outputs can be translated into signals with names
like "State0," "State1," ... "State9."
(No gates needed; just draw a block and tell what it is; label all
inputs and outputs meaningfully.) (B) Given these ten "State"
signals, show the gates to implement the ALUSelA control signal. HINT:
ALUSelA is zero in states 0 and 1, and is one in all other states
except state 9, where it is not specified. It will be easier to draw
the gates to generate a one when ALUSelA must be zero, and then to
invert that.
Christopher Vickery
Computer Science Department
Queens College of CUNY